PARTHENON User's Manual

These are written for MS-DOS version of PARTHENON. Please take notice of the difference between MS-DOS version and Workstation when Workstation users refer to this manual


1. Introduction to PARTHENON
2. Introduction to Designing with PARTHENON

Description Language

3. Hardware Description Language : SFL
Description Examples by SFL
4. Netlist and Cell Library Description Languages : NLD and PCD
Description Examples by PCD

Program Manual

5. SFL Behavioral Simulator : SECONDS
6. Logic Synthesizer : SFLEXP
7. Technology Mapper & Logic Circuit Optimizer : OPT_MAP
8. Combinational Circuit Simplifier : ONSET
9. Reducer for Logic Inverters : RINV
10. Circuit Diagram Generator : NLD_PS

More Information about PARTHENON

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