What is the auto command?
You have experienced logic synthesis with an example. The auto command plays an important role in simplifying the use of the program with all but the most simple examples. Understand this command and you have come close to understanding how to use the logic synthesis programs of PARTHENON.
When the auto command is entered, a batch file called "auto.bat" existing under %PARTHENON%\com (%PARTHENON% is the path name used to install PARTHENON) is executed. This batch file executes a series of the logic synthesis programs of PARTHENON in a typical order. You can understand the standard usage of the synthesis programs by reading the content of "auto.bat" and tracing its behavior. Since "auto.bat" is an ordinary batch program, it can be customized. If you want to control the degree of optimization of synthesized circuits, you may have to rewrite parts of the batch program. This section describes how "auto.bat" works, assuming the standard version, generated when PARTHENON is installed.
Process flow assumed by "auto.bat"
Figure 2.6 shows the series of processes assumed by "auto.bat". In this chart, module_name represents the name of the top module (specified as the first parameter of "auto.bat") of the circuit to be synthesized.
<Fig2.6> Synthesis flow assumed by "auto.bat"
(1) Logic synthesis program SFLEXP is first activated. It synthesizes an HSL-formatted netlist, module_name.hs1, from an SFL source, module_name.sfl.
During the execution of SFLEXP, processing programs PRIME and NEGATE are repeatedly activated as necessary.
(2) Netlist format conversion program, HSL_NLD, creates an NLD-formatted netlist in a sub-directory, module_name.lst.
The top module, module_name.nld, always exists. In addition, sub-module files, sub-module-name.nld, are generated. Since the NLD-formatted netlist is created in separate files, each corresponding to a sub-module in the hierarchical structure, there can be more than one file in sub-directory, module_name.lst (this sub-directory is provided to prevent confusion).
(3)Circuit optimization program, OPT_MAP, is then activated. It simplifies the logic circuits at the logic level, unrelated to specific technologies (physical information in a cell library).
OPT_MAP is started either by entering commands interactively or by a script file describing the OPT_MAP command sequence. The latter method is adopted here. A template file opt_scr.op1 is in a directory of the cell library (shown as cell_lib in Figure 2.6) specified by the third parameter of "auto.bat" in order to automatically generate the script file. The script file, module_name.op1, to be used by OPT_MAP is generated from this template file.
Furthermore, another script file, module_name.ons, is called by module_name.op1 and executed. This module_name.ons is also generated from a template file, opt_scr.lv3, in the cell library. OPT_MAP executes module_name.ons. The latter repeatedly activates the logic circuit simplification program, ONSET. Clearly redundant parts are thus removed from the circuit, and the logic combinational circuit parts are simplified. The resulting netlist from OPT_MAP is stored in NLD format in a sub-directory, module_name.2nd.
(4) The logic circuit derived thus far still has room for global optimization. Polarity optimization (reduction in inverters) is performed by RINV, which is efficient enough to be applicable to a large-scale circuit. RINV reads the netlist from module_name.2nd, optimizes the polarity in the whole circuit, and stores the result in NLD format in the sub-directory, module_name.3rd.
(5) Circuit optimization program, OPT_MAP, is activated again. This time, script file module_name.op2 is used for optimization to take into consideration external conditions and physical conditions for the real cells (delay time, load drive capacity, areas, etc.). This command script performs mapping onto real cells, evaluates delay, etc. Combinational circuits including critical paths are identified, and the script file, module_name.cpb, is called to execute the logic circuit simplification program ONSET, which recompresses critical paths. This optimization process is repeated by the script.
The script files, module_name.op2 and module_name.cpb, are automatically generated from the template files, opt_scr.op2 and opt_scr.cpb respectively, in the cell library. In the end, the netlist for the final circuit satisfying the constraints is stored in NLD format in the sub-directory, module_name.4th. In addition, netlist module_name.edf in EDIF format is generated in the current directory.
(6) The circuit diagram generation program, NLD_PS, generates a PostScript-formatted circuit diagram from the NLD-formatted file in module_name.4th and stores it in the current directory with the file name, module_name.ps.
The character string replacement program, SRP, is used to generate script files for OPT_MAP from template files.
Cell library structure assumed by "auto.bat"
The execution of "auto.bat" assumes that the cell library it uses has such sub-directories as start, start_e, cell, and cell_e. This section briefly describes the reason for this (for detail, see Section 4.3, "Making Cell Library"). The library for demonstration, celldemo, which is generated when PARTHENON is installed is a typical example of such a libarary.
(1) Sub-directory "cell" for storing real cell information
Real cell information including physical information is stored in PCD format (file name is module-name.pcd) in a sub-directory cell. The final netlist is the information on connections between the instances (individual parts) created from these real cells as classes (part types).
(2)Sub-directory "start" for storing virtual cells
The types, module names, terminal names, etc. of real cells provided naturally differ from one cell library to another. Therefore, in the earlier stages of circuit synthesis, where circuits are still technology-independent, PARTHENON uses cell types (basic gate, flip-flop, etc.) and their names (inv-, nand--2, reg--1, and other reserved cell names), which are independent of real cell types and names so that they can be handled in a common manner by different processing programs. The netlists synthesized by SFLEXP and those generated by ONSET and RINV contain information on the connections between instances created from these virtual cells as classes.
It would be convenient if netlists of virtual cells could be handled by processing programs in a consistent manner, as netlists of real cells are. Information on virtual cells is therefore also provided in a cell library. The sub-directory, start, is provided for this purpose. Information on all cells with reserved names must be stored there in PCD or NLD format (file names are module-name.pcd and module-name.nld). NLD is used when real cells with the same functions as those of virtual cells do not exist. In such a case, the same functions must be implemented by adding other cells to the netlist.
(3)Sub-directories, cell_e and start_e, for functional units
In addition to the real cells provided as standard, sub-directories, cell_e and start_e, are provided to store information on real cells, such as hardware macros, and corresponding virtual cells for the designer to use as functional "circuits."
-Using "auto.bat"
When activating "auto.bat", you can specify up to 4 parameters as shown below.
These parameters are specified as follows
When, for example, synthesis is to be performed with the module, TIMER, as the top module from the SFL source file, TIMER.sfl, use TIMER as the module_name. If you want to execute down to the generation of a logic circuit diagram, specify ps as the goal and all the steps from SFLEXP to NLD_PS are executed sequentially. You can specify the cell library, celldemo (which must have been placed in %PARTHENON%\celldemo) attached to PARTHENON, for cell_lib. Mode can be omitted. This will yield the execution example (6) (p. 2-25), shown at the beginning of Section 2.3:
A>auto TIMER ps celldemo
Specifying quick for the mode skips the PRIME, NEGATE and ONSET processes. In this case, SFLEXP is executed with the option of -nopost to skip the PRIME and NEGATE processes. When an SFL description with a hierarchical structure (with sub-modules) is to be synthesized, specifying this option may generate unexpected loop circuits (SFLEXP itself terminates normally, but, in a later process, OPT_MAP may not be able to evaluate delay, or other problems may occur). Accordingly, it is recommended not to use SFLEXP with a quick option. Skipping ONSET in the execution of OPT_MAP only skips the logic circuit simplification process and causes no problems.
Reading the content of "auto.bat"
Use your editor to browse the content of "auto.bat" in %PARTHENON%\com. Although the many if-statements and goto-statements unrelated to the essence of logic synthesis processing in the file may be distracting at first glance, you should be able to understand the content without difficulty, provided you have some familiarity with batch file commands (for detail, refer to any MS-DOS manual).
The numerous if-statements and goto-statements are there to check the correctness of parameters (referred to as %1, %2, %3 and %4 in the batch file) and to activate correspondent programs. For example,
A>auto TIMER nld1 celldemo
terminates the process at the stage where an initial netlist is generated in sub-directory, TIMER.1st.
In addition, many control statements are there to ensure that the operation starts at the necessary point, by skipping processes already executed. For example, if the final netlist has been completed by
A>auto TIMER nld4 celldemo
then
A>auto TIMER ps celldemo
skips the previously executed processes from SFLEXP to OPT_MAP and immediately starts the NLD_PS process.
When, for example, you wish to start again at the 1st OPT_MAP process because TIMER.ons has been modified, you need only to delete the output file of the process you want to re-execute. In this case,
A>del TIMER.2nd\*.* A>auto TIMER ps celldemo
skips the processes from SFLEXP to HSL_NLD and activates the series of processes from OPT_MAP to NLD_PS.
Let's try to look at only the essential command sequence by excluding if-statements, goto-statements, echo-statements and other execution control statements. Let's extract the essential command sequence in the example shown in Item (6) at the beginning of Section 2.3:
A>auto TIMER ps celldemo
The result is shown in List 2.11 (mixing symbols \ and / as delimiters of directories causes no problem).
Understanding the essence of auto
The essence of auto, i.e., the typical use of the synthesis programs of PARTHENON, is condensed into 16 lines in List 2.11.
<List 2.11> Command sequence example to be executed with "auto.bat"
1: sflexp TIMER.sfl TIMER.hsl
2: mkdir TIMER.1st
3: hsl_nld TIMER.hsl TIMER.1st
4: srp TargeT TIMER A:\par\celldemo\opt_scr.op1 > TIMER.op1
5: srp TargeT TIMER A:\par\celldemo\opt_scr.lv3|srp InputpiN 12 > TIMER.ons
6: srp TargeT TIMER A:\par\celldemo\opt_scr.lv3|srp InputpiN 12 >> TIMER.ons
7: mkdir TIMER.2nd
8: echo TIMER.op1|opt_map TIMER TIMER.1st A:\par/sfl_lib.dir A:\par/celldemo/start
A:\par/celldemo/start_e
9: mkdir TIMER.3rd
10: rinv TIMER TIMER.2nd A:\par/celldemo/start A:\par/celldemo/start_e -w TIMER.3rd
11: srp TargeT TIMER A:\par\celldemo\opt_scr.op2 > TIMER.op2
12: srp TargeT TIMER A:\par\celldemo\opt_scr.cpb|srp InputpiN 10 > TIMER.cpb
13: srp TargeT TIMER A:\par\celldemo\opt_scr.cpb|srp InputpiN 10 >> TIMER.cpb
14: mkdir TIMER.4th
15: echo TIMER.op2 | opt_map TIMER TIMER.3rd A:\par/celldemo/start A:\par/celldemo/s
tart_e A:\par/celldemo/cell
16: nld_ps -c "PARTHENON v2.3" -p 1.2 -s A4 -o TIMER.ps TIMER TIMER.4th A:\par/celld
emo/cell A:\par/celldemo/cell_e
auto TIMER ps celldemo
Further explanation will be necessary for lines 4 to 6 and lines 11 to 13, where script files are generated, and these are given below. You should easily understand all the other parts if you also read the explanation on the activation options of each program.
Understanding the script file for OPT_MAP
This section briefly describes the important parts of the four types of script file for OPT_MAP generated in lines 4 to 6 and lines 11 to 13 of List 2.11. These four files remain after the execution of example (6) shown at the beginning of Section 2.3. Use an editor to browse them. They contain command sequences for OPT_MAP.
(1) Important operations for TIMER.op1 are removal of clearly redundant portions of the circuit with the 'rm' command, calling the external script file TIMER.ons, and storing the resulting netlist in TIMER.2nd using the 'write_org_type' command.
(2) TIMER.ons first flattens the entire hierarchy using the 'flat' command and then encloses combinatorial logic circuits, each having a maximum of 12 inputs, by means of the 'encia' command. Then the 'eachn' command generates a temporary script file TIMER._tp which applies ONSET to simplify the each enclosed logic circuit. TIMER._tp is called and executed, and then, the enclosure is released with the 'dise' command. This entire process is repeated once more.
ONSET interfaces for TIMER._tp execution are as follows. A BLIF-formatted netlist is used for output from the OPT_MAP, and an NLD-formatted netlist file is used for output from ONSET, both of these being in temporary sub-directory TIMER._dr. A temporary batch file _tmp.bat is created and executed to activate ONSET from OPT_MAP.
The temporary file _tmp.bat specifies %PARTHENON%/com/onset.dir/b2n_area.scr as the script file to be executed by ONSET. In addition, it specifies a netlist path name as the first parameter, and 'on' as the second parameter. These parameters are referred to by b2n_area.scr executed by ONSET and, as a result, ONSET calls %PARTHENON%/com/onset.dir/area.scr to execute area minimization.
(3) TIMER.op2 sets design conditions after the execution of 'flat,' 'rm,' etc. The 'init pin' command and the 'set' command set an event for the starting point of the delay calculation, at an external input terminal. The 'max' command specifies restrictions on the load capacity of a part of the external input terminals. In addition, the 'setv' command puts a value to the OPT_MAP global variable, ?cycle. This variable, ?cycle, appears in the description of restrictions, such as flip-flop setup time and hold time, in the description of the cell library, celldemo. When this library is being used, it is treated as being equivalent to cycle time.
After these conditions are set, the 'opt' command is executed to optimize the circuit in such a way as to resolve all restrictions. If the 'opt' command is executed only once, some restrictions may remain unresolved; therefore, the command is executed three times here (The execution of the opt command has no effect after all violations of restrictions have been cleared).
After an external script file, TIMER.cpb, has been called, the 'last_org_type' command stores the final netlist in TIMER.4th, and the 'edif' command generates an EDIF-formatted netlist as TIMER.edf.
(4) As is the case with TIMER.ons, TIMER.cpb is an OPT_MAP script file for activating ONSET. However, unlike TIMER.ons, TIMER.cpb uses the 'encid' command, whichencloses modules found to be in the maximum delay transmission path, and applies ONSET based on a speed-priority script file. Since the partial circuits subjected to ONSET are built with virtual cells, the 'opt' command must be executed afterwards.
Note that the values set in TIMER.op2 are arbitrary. In synthesizing an actual LSI, an appropriate cell library should be created, and constraints reflecting the actual conditions should be set. The script files generated by auto should be used as templates only.
Changing the script file for OPT_MAP
The contents of the two script files TIMER.ons and TIMER.cpb, generated by,
A> auto TIMER ps celldemo quick
with quick mode specified are quite different from the content of the files without quick mode specified. When quick mode is specified, ONSET is not executed at all.
This may be an extreme example, but the script file can be adjusted to control the way ONSET is applied.
The commands shown in lines 5 and 6 in List 2.11 enclose combinational circuits and twice apply ONSET to such circuits. Repeat line 6 to generate TIMER.ons as shown below, resulting in the application of ONSET three times.
srp TargeT TIMER A:\par\celldemo\opt_scr.lv3|srp InputpiN 12 > TIMER.ons srp TargeT TIMER A:\par\celldemo\opt_scr.lv3|srp InputpiN 12 >> TIMER.ons srp TargeT TIMER A:\par\celldemo\opt_scr.lv3|srp InputpiN 12 >> TIMER.ons
In practice, the modification of "auto.bat" is reflected in script files that are generated with it afterwards.
In these commands, InputpiN is replaced with 12, which indicates the maximum number of input terminals of the combinational circuits to be enclosed. If this value is increased (31 at maximum), ONSET can be applied to larger circuits at one time (although simplification may take an extremely long time in such cases).
In most cases, if circuits are enclosed with about 15 input terminals, and the execution is repeated about 5 times, further attempts at simplification yield no effect. Of course, there are exceptional logic circuits. Various methods should be tried for such circuits to achieve the best results.
For small combinational circuits such as those included in the TIMER example, sufficient simplification is achieved with a single application of ONSET; further repetition is of no avail.
The commands in lines 12 and 13 of List 2.11 are used to apply ONSET to the parts considered to be critical paths. In a manner similar to the above, the relevant part of "auto.bat" can be modified to control repetition. To achieve higher performance with your circuit, however, it is advisable to use OPT_MAP interactively to fine-tune your optimization.
Besides modifying "auto.bat" as shown above, try to adjust the generated script files or the original template files, or try to change the script file executed by ONSET. In the event that these files become corrupted, they can be restored to their original state by reinstalling PARTHENON.
Changing "auto.bat" drastically
The purpose of "auto.bat" is to provide a guideline for standard use of PARTHENON synthesis programs. If you do not wish to follow the guideline, you can change it manually.
For example, the polarity optimization program, RINV, is not essential in synthesis. If you do not use RINV, you need not execute OPT_MAP in two separate occasions, and thus you can simplify the process. If you create "auto.bat" and template files for such a simplified process, you can test the effect with an experiment. Of course, you can give the created file a different name so that it can coexist with the existing "auto.bat". You can then apply either of them selectively as the situation demands.
It is also possible to execute the circuit diagram generation program, NLD_PS, to output circuit diagrams after each process (circuit diagrams consisting of virtual cells can also be generated). If you have a PostScript viewer, you can arrange for automatic activation of the viewer.
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