SFL MANUAL

3.14 Format of the SFL Language

The SFL language format is given below. The notation of BNF (Backus-Naur Form) in Table 3.5 is used. For example, {x1|x2|x3} indicates "x1, x2 or x3 is repeated 0 or more times," and [x1|x2|x3] indicates "x1, x2 or x3 can be omitted."

<Table 3.5> Notation of BNF

Symbol

Symbol ::= Name|Number|Constant|KeyWord|ReservedWord

Name ::= AlphabeticCharacter{AlphabeticCharacter|NumericCharacter}

Number ::= NumericCharacter{NumericCharacter}

Constant ::= 0{xHexadecimalNumber|oOctalNumber|bBinaryNumber|XHexadecimalNumber|OOctalNumber|BBinaryNumber}

HexadecimalNumber ::= {HexadecimalNumericCharacter}

OctalNumber ::= {OctalNumericCharacter}

BinaryNumber ::= {BinaryNumericCharacter}

KeyWord ::= module|circuit|declare

		|input|output|bidirect

		|instrin|instrout|instrself

		|sel|bus|sel_v|bus_v

		|reg|reg_ws|reg_wr|mem

		|instr_arg|stage_name|task

		|instruct|stage

		|state_name|segment_name|first_state

		|state|segment

		|par|alt|any|if|else

		|goto|call|return|generate|relay|finish

		|'{|'}|;|,|(|)|.|:|'[|']

		|:=|=|==|'||@|&|'|'||+|'>|'<

		|'>'>|'<'<|^|/'||/@|/&|/|\|#

ReservedWord ::= p_reset|m_clock|s_clock|b_clock|VDD|VSS

		|scan_in|scan_out|scan_enb|scan_clock|t_adrs_Number

AlphabeticCharacter ::= A|B|C|D|E|F|G|H|I|J|K|L|M|N|O|P|Q|R|S|T|U|V|W|X|Y|Z

		|a|b|c|d|e|f|g|h|i|j|k|l|m|n|o|p|q|r|s|t|u|v|w|x|y|z|_

BinaryNumericCharacter ::= 0|1

OctalNumericCharacter ::= 0|1|2|3|4|5|6|7

NumericCharacter ::= 0|1|2|3|4|5|6|7|8|9

HexadecimalNumericCharacter ::= 0|1|2|3|4|5|6|7|8|9|a|b|c|d|e|f|A|B|C|D|E|F

SpecificCharacter ::= !|"|#|$|%|&|'|(|)|*|+|,|-|.|/|:|;

	   |'<|=|'>|?|@|'[|\|']|^|`|'{|'||'}|~

SpaceCharacter ::= (space)|(tab)|(newline)

One or more spaces are necessary to delimit Symbols. However, in the case of SpecificCharacter strings, if a part of a string corresponds to a longest possible key word, that part is considered a Symbol, and no SpaceCharacter is required before and after such Symbols. For example, ":===" is considered to be a combination of ":=" and "==".

For the AlphabeticCharacter at the beginning of a Name, "_" is not allowed.

ReservedWords are the fixed names of external terminals used in synthesized circuits. Table 3.6 briefly explains ReservedWords and shows what programs generate them (The ReservedWords related to "scan" and "test" in the right part of the table are valid when the test synthesis function provided only in the workstation version of PARTHENON is used.) Refer to Section 6.3 for details of how to use reset and clock-related terminals generated by SFLEXP. Names identical to KeyWords and ReservedWords are not allowed.

<Table 3.6> Reserved words at the SFL level for use in logical composition

SFL description

SFLDescription ::=

	{DeclarationOfModule|DefinitionOfModule|DefinitionOfFunctionalCircuit}

DeclarationOfModule ::=

	declare ModuleName '{

		{DefinitionOfExternalTerminal}

		{DefinitionOfDummyArgumentForControlTerminalBeingUsed}

	'}

DefinitionOfExternalTerminal ::=

	  input DataInputTerminalName['<BitWidth'>]{,DataInputTerminalName['<BitWidth'>]};

	| output DataOutputTerminalName['<BitWidth'>]{,DataOutputTerminalName['<BitWidth'>]};

	| bidirect BidirectionalDataTerminalName['<BitWidth'>]{,BidirectionalDataTerminalName['<BitWidth'>]};

	| instrin ControlInputTerminalName{,ControlInputTerminalName};

	| instrout ControlOutputTerminalName{,ControlOutputTerminalName};

DefinitionOfDummyArgumentForControlTerminalBeingUsed ::=

	instr_arg ControlInputTerminalName([TerminalNameForInput{,TerminalNameForInput}]);

DefinitionOfModule ::=

	module ModuleName '{

		{DeclarationOfModule}

		{DefinitionOfExternalTerminal|DefinitionOfComponentElement}

		{DefinitionOfControlTerminalDummyArgument}

		{DefinitionOfStageAndTaskAndDummyArgument}

		[DefinitionOfCommonOperation]

		{DefinitionOfControlTerminalOperation}

		{DefinitionOfStageOperationProcedure}

	'}

DefinitionOfFunctionalCircuit ::=

	circuit FunctionalCircuitName '{

		{DeclarationOfModule}

		{DefinitionOfExternalTerminal|DefinitionOfComponentElement}

		{DefinitionOfControlTerminalDummyArgument}

		{DefinitionOfStageAndTaskAndDummyArgument}

		[DefinitionOfCommonOperation]

		{DefinitionOfControlTerminalOperation}

		{DefinitionOfStageOperationProcedure}

	'}

When an argument does not exist,DefinitionOfDummyArgumentForControlTerminalBeingUsed can be omitted.

Component elements

DefinitionOfComponentElement ::=

	  instrself InternalControlTerminalName{,InternalControlTerminalName};

	| bus InternalDataTerminalName['<BitWidth'>]{,InternalDataTerminalName['<BitWidth'>]};

	| sel InternalDataTerminalName['<BitWidth'>]{,InternalDataTerminalName['<BitWidth'>]};

	| bus_v InternalDataTerminalName['<BitWidth'>]{,InternalDataTerminalName['<BitWidth'>]};

	| sel_v InternalDataTerminalName['<BitWidth'>]{,InternalDataTerminalName['<BitWidth'>]};

	| reg RegisterName['<BitWidth'>]{,RegisterName['<BitWidth'>]};

	| reg_ws RegisterName['<BitWidth'>]{,RegisterName['<BitWidth'>]};

	| reg_wr RegisterName['<BitWidth'>]{,RegisterName['<BitWidth'>]};

	| mem MemoryName'[NumberOfWords']['<BitWidth'>]{,MemoryName'[NumberOfWords']['<BitWidth'>]};

	| ModuleName Sub-moduleName{,Sub-moduleName};

Dummy argument

DefinitionOfControlTerminalDummyArgument ::=

	  instr_arg ControlOutputTerminalName([TerminalNameForOutput{,TerminalNameForOutput}]);

	| instr_arg Sub-moduleName.ControlInputTerminalName([TerminalNameForInput{,TerminalNameForInput}]);

	| instr_arg InternalControlTerminalName([InternalDataTerminalName{,InternalDataTerminalName}]);

TerminalNameForInput ::=

	  DataInputTerminalName

	| BidirectionalDataTerminalName

TerminalNameForOutput ::=

	  DataOutputTerminalName

	| BidirectionalDataTerminalName

DefinitionOfStageAndTaskAndDummyArgument ::=

	stage_name StageName '{

		{task TaskName([RegisterName{,RegisterName}]);}

      '}

When an argument does not exist, the DefinitionOfControlTerminalDummyArgument can be omitted.

Subject of operation

DefinitionOfCommonOperation ::= Operation

DefinitionOfControlTerminalOperation ::=

	  instruct ControlInputTerminalName Operation

	| instruct InternalControlTerminalName Operation

	| instruct Sub-moduleName.ControlIutputTerminalName Operation

DefinitionOfStageOperationProcedure ::=

	stage StageName '{

		{DefinitionOfStateName}

		{DefinitionOfSegmentName}

		[DefinitionOfInitialState]

		[DefinitionOfCommonOperation]

		{DefinitionOfStateOperation}

		{DefinitionOfSegmentOperationProcedure}

	'}

DefinitionOfSegmentOperationProcedure ::=

	segment SegmentName '{

		{DefinitionOfStateName}

		DefinitionOfInitialState

		[DefinitionOfCommonOperation]

		{DefinitionOfStateOperation}

	'}

DefinitionOfStateName ::= state_name StateName{,StateName};

DefinitionOfSegmentName ::= segment_name SegmentName{,SegmentName};

DefinitionOfInitialState ::= first_state StateName;

DefinitionOfStateOperation ::= state StateName Operation

When a stage is used without segment or state being specified, DefinitionOfInitialState can be omitted.

Operation

Operation ::=

	  ParBlock

	| AltBlock

	| AnyBlock

	| IfBlock

	| UnitOeration

ParBlock ::= par'{{Operation}'}

AltBlock ::= alt'{ConditionalOperation{ConditionalOperation}[ElseOperation]'}

AnyBlock ::= any'{ConditionalOperation{ConditionalOperation}[ElseOperation]'}

IfBlock ::= if(Condition)Operation

ConditionalOperation ::= Condition:Operation

ElseOperation ::= else:Operation

Condition ::= Expression

Unit operation

UnitOperation ::=

	  OutputOfValueToTerminal

	| WriteToRegister

	| WriteToMemory

	| StateTransition

	| SegmentCall

	| SegmentCallWithoutSpecifyingReturnState

	| ReturnFromSegment

	| JobGeneration

	| JobTransfer

	| JobFinish

        | ActivationOfControlTerminal

	| BlankStatement

OutputOfValueToTerminal ::=

	  InternalDataTerminalName=Expression;

	| DataOutputTerminalName=Expression;

	| BidirectionalDataTerminalName=Expression;

	| Sub-moduleName.DataOutputTerminalName=Expression;

	| Sub-moduleName.BidirectionalDataTerminalName=Expression;

WriteToRegister ::= RegisterName:=Expression;

WriteToRegister ::= MemoryName'[Expression']:=Expression;

StateTransition ::= goto StateName;

SegmentCall ::= call SegmentName(ReturnStateName);

SegmentCallWithoutSpecifyingReturnState ::= call SegmentName();

ReturnFromSegment ::= return;

JobGeneration ::= generate StageName.TaskName([ActualArgument{,ActualArgument}]);

JobTransfer ::= relay StageName.TaskName([ActualArgument{,ActualArgument}]);

JobFinish ::= finish;

ControlTerminalActivation ::=

	  ControlOutputTerminalName([ActualArgument{,ActualArgument}]);

	| Sub-moduleName.ControlInputTerminalName([ActualArgument{,ActualArgument}]);

	| InternalControlTerminalName([ActualArgument{,ActualArgument}]);

BlankStatement ::= ;

ReturnStateName ::= StateName

ActualArgument ::= Expression

Blank statements are used as ,

alt {

    a : ;

    b : ;

    else : goto x ;

}

This means that "if neither 'a' nor 'b', state transition to 'x' takes place."

Expression and operator

Expression ::=

	  Monomial'|Expression	/* OR */

	| Monomial@Expression	/* Exclusive-OR */

	| Monomial&Expression	/* AND */

	| Monomial'|'|Expression	/* concatenation */

	| Monomial+Expression	/* addition */

	| Monomial'>'>Expression	/* bit right shift  */

	| Monomial'<'<Expression	/* bit left shift  */

	| Monomial==Expression	/* equivalence operation  */

	| Monomial

Monomial ::=

	  ^Monomial	/* negation  */

	| /'|Monomial	/* OR in the bit direction */

	| /@Monomial	/* Exclusive-OR in the bit direction  */

	| /&Monomial	/* AND in the bit direction */

	| /Monomial	/* decode  */

	| \Monomial	/* encode */

	| NumberOfResultDigits#Monomial	/* sign extension */

	| Element'<MSBPosition[:LSBPosition]'>	/* bit extraction */

	| Element

Elements

Element ::=

	  (Expression)

	| Constant

	| RegisterName

	| MemoryName'[Address']

	| StageName.TaskName

	| InternalDataTerminalName

	| InternalControlTerminalName

	| DataInputTerminalName

	| DataOutputTerminalName

	| BidirectionalDataTerminalName

	| ControlInputTerminalName

	| ControlOutputTerminalName

	| Sub-moduleName.DataInputTerminalName

	| Sub-moduleName.DataOutputTerminalName

	| Sub-moduleName.BidirectionalDataTerminalName

	| Sub-moduleName.ControlInputTerminalName

	| Sub-moduleName.ControlOutputTerminalName

	| Sub-moduleName.ControlInputTerminalName([ActualArgument{,ActualArgument}]).DataOutputTerminalName

	| Sub-moduleName.ControlInputTerminalName([ActualArgument{,ActualArgument}]).BidirectionalDataTerminalName

	| InternalControlTerminalName([ActualArgument{,ActualArgument}]).InternalDataTerminalName

	| ControlOutputTerminalName([ActualArgument{,ActualArgument}]).DataInputTerminalName

	| ControlOutputTerminalName([ActualArgument{,ActualArgument}]).BidirectionalDataTerminalName

address ::= Expression

Names and numbers

ModuleName ::= Name

FunctionalCircuitName ::= Name

DataInputTerminalName ::= Name

DataOutputTerminalName ::= Name

BidirectionalDataTerminalName ::= Name

InternalDataTerminalName ::= Name

ControlInputTerminalName ::= Name

ControlOutputTerminalName ::= Name

InternalControlTerminalName ::= Name

Sub-moduleName ::= Name

RegisterName ::= Name

MemoryName ::= Name

StageName ::= Name

TaskName ::= Name

SegmentName ::= Name

StateName ::= Name

BitWidth ::= Number

NumberOfWords ::= Number

NumberOfResultDigits ::= Number

MSBPosition ::= Number

LSBPosition ::= Number

ModuleNames and FunctionalCircuitNames must be unique throughout the design. Module component elements names, i.e., DataInputTerminalNames, DataOutputTerminalNames, BidirectionalDataTerminalNames, InternalDataTerminalNames, ControlInputTerminalNames, ControlOutputTerminalNames, InternalControlTerminalNames, Sub-moduleNames, RegisterNames, MemoryNames, StageNames must be unique within the given module. In addition, TaskNames, SegmentNames, and StateNames must be unique within the given stage, and StateNames defined in the segment must be unique within the given segment.

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