Trial experience of logic synthesis
Let's try logic synthesis of the SFL description whose behavior has been checked in simulation by SECONDS. As examples, we will use the two SFL source files described in section 2.1 as they are: List 2.1 as TIMER.sfl and List 2.9 as DECR8.sfl. These SFL source files are stored in directory 'example.dir`chapter2' where PARTHENON itself has been installed, so they are ready to use. Note, however, that many working files will be generated in the current directory when logic synthesis is performed. We will therefore make a work directory somewhere on the hard disk and copy the SFL source files there. We will use the files in the work directory in the following operations.
Let's assume that the two SFL source files TIMER.sfl and DECR8.sfl exist in the current directory. Enter the following commands in sequence at the MS-DOS command prompt.
The first and second parameters of 'auto' commands in Items (1), (2) and (4) below specify the applicable modules and processing content. They are case sensitive. Enter the following.
A>auto TIMER nld1 celldemo ................(1) A>auto DECR8 nld1 celldemo ................(2) A>copy DECR8.1st\DECR8.nld TIMER.1st ......(3) A>auto TIMER ps celldemo ..................(4)As you enter each 'auto' command in (1), (2) and (4), the logic synthesis programs of PARTHENON will be activated and many messages indicating the processing content will be displayed on the screen. The details of these messages will be explained later. When all these commands have been successfully executed, you have completed logic synthesis, optimization, technology mapping, generation of final netlist and generation of logic circuit diagram. Isn't it much simpler than you expected?
Generated file
When the series of operations (1) to (4) have been completed, you will find several files and sub-directories generated in the current directory (Figure 2.4). Of these files and directories, TIMER.edf is the final result of logic synthesis. It is a netlist (information on parts connection) in the industry-standard EDIF format. This file can be read by various types of placement/routing tools to fabricate an LSI chip.
<Fig2.4> > Directory content after the completion of 'auto' command (Displayed with dir/od command)
A TIMER.ps file is also generated. It is a logic circuit diagram in PostScript format. If you have a PostScript printer, print the file.
A>type TIMER.ps >prn
If you enter the above command, the circuit diagram shown in Figure 2.4 will be printed out. If a PostScript viewer, such as Ghostscript, is available, you can display the circuit diagram on the screen. In a matter of a few minutes (depending on the type of PC) after writing an SFL description, you can get a logic circuit diagram. Furthermore, you are assured that the obtained circuit will behave properly.
<Fig2.5> > TIMER.ps printer output (A4-size format is used)
Deleting generated files to return to pre-systhesis state
Let's try to delete the generated files and sub-directories and return to the pre-synthesis state.
A>auto TIMER clean A>auto DECR8 clean
The message "Directory to be deleted does not exist" will be displayed. Ignore it. Only the TIMER.sfl and DECR8.sfl files remain.
Simpler procedure
Logic synthesis can be completed more easily if SFL sources are put together in a single file. Taking the analogy of a programming language, procedures (1) to (4) are like separate compilations while the simpler procedure below is like a batch compilation.
For that purpose, FLS sources are put together into a file. (The contents of DECR8.sfl are appended to those of TIMER.sfl.)
A>type DECR8.sfl >> TIMER.sfl ...........(5)
This command rewrites TIMER.sfl so that it will contain all SFL descriptions for the module TIMER. Then, the synthesis operation is completed by simply entering:
A>auto TIMER ps celldemo ................(6)
(Note that, if the results of a previous synthesis remain, the system does not re-synthesize files. Clear the previous results with auto TIMER clean in advance.) A logic circuit the same as the one synthesized earlier will be synthesized.
Of course, when you determine the file structure of the SFL sources, you should consider the possibility of reusing module parts. You should not always put files together just for simplicity of the synthesis operation.
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