/**************************************** * SRIP用メモリモジュール * * newcpu.sfl にインクルードして使用 * ****************************************/ module main { submod_type newcpu { instrin reset ; instrout i_read ; output ir_adrs<32> ; input ir_data<32> ; instrout o_read ; instrout o_write ; output ow_loc<4> ; output rw_adrs<32> ; input or_data<32> ; output ow_data<32> ; } circuit_type i_memory { input adrs<30> ; output r_data<32> ; mem cell[134217728]<32> ; mem cell_1[134217728]<32> ; mem cell_2[134217728]<32> ; mem cell_3[134217728]<32> ; mem cell_4[134217728]<32> ; mem cell_5[134217728]<32> ; mem cell_6[134217728]<32> ; mem cell_7[134217728]<32> ; instrin read ; instr_arg read(adrs) ; instruct read any { (^adrs<29>) & (^adrs<28>) & (^adrs<27>) : r_data = cell[adrs<26:0>] ; (^adrs<29>) & (^adrs<28>) & ( adrs<27>) : r_data = cell_1[adrs<26:0>] ; (^adrs<29>) & ( adrs<28>) & (^adrs<27>) : r_data = cell_2[adrs<26:0>] ; (^adrs<29>) & ( adrs<28>) & ( adrs<27>) : r_data = cell_3[adrs<26:0>] ; ( adrs<29>) & (^adrs<28>) & (^adrs<27>) : r_data = cell_4[adrs<26:0>] ; ( adrs<29>) & (^adrs<28>) & ( adrs<27>) : r_data = cell_5[adrs<26:0>] ; ( adrs<29>) & ( adrs<28>) & (^adrs<27>) : r_data = cell_6[adrs<26:0>] ; ( adrs<29>) & ( adrs<28>) & ( adrs<27>) : r_data = cell_7[adrs<26:0>] ; } } circuit_type o_memory { input adrs<30> ; input byte_loc<4> ; /* Remark! order & meaning */ input w_data<32> ; output r_data<32> ; mem cell0[134217728]<8> ; mem cell1[134217728]<8> ; mem cell2[134217728]<8> ; mem cell3[134217728]<8> ; mem cell0_1[134217728]<8> ; mem cell1_1[134217728]<8> ; mem cell2_1[134217728]<8> ; mem cell3_1[134217728]<8> ; mem cell0_2[134217728]<8> ; mem cell1_2[134217728]<8> ; mem cell2_2[134217728]<8> ; mem cell3_2[134217728]<8> ; mem cell0_3[134217728]<8> ; mem cell1_3[134217728]<8> ; mem cell2_3[134217728]<8> ; mem cell3_3[134217728]<8> ; mem cell0_4[134217728]<8> ; mem cell1_4[134217728]<8> ; mem cell2_4[134217728]<8> ; mem cell3_4[134217728]<8> ; mem cell0_5[134217728]<8> ; mem cell1_5[134217728]<8> ; mem cell2_5[134217728]<8> ; mem cell3_5[134217728]<8> ; mem cell0_6[134217728]<8> ; mem cell1_6[134217728]<8> ; mem cell2_6[134217728]<8> ; mem cell3_6[134217728]<8> ; mem cell0_7[134217728]<8> ; mem cell1_7[134217728]<8> ; mem cell2_7[134217728]<8> ; mem cell3_7[134217728]<8> ; instrin read ; instrin write ; instr_arg read(adrs) ; instr_arg write(adrs, byte_loc, w_data) ; instruct read any { (^adrs<29>) & (^adrs<28>) & (^adrs<27>) : r_data = cell0[adrs<26:0>] || cell1[adrs<26:0>] || cell2[adrs<26:0>] || cell3[adrs<26:0>] ; (^adrs<29>) & (^adrs<28>) & ( adrs<27>) : r_data = cell0_1[adrs<26:0>] || cell1_1[adrs<26:0>] || cell2_1[adrs<26:0>] || cell3_1[adrs<26:0>] ; (^adrs<29>) & ( adrs<28>) & (^adrs<27>) : r_data = cell0_2[adrs<26:0>] || cell1_2[adrs<26:0>] || cell2_2[adrs<26:0>] || cell3_2[adrs<26:0>] ; (^adrs<29>) & ( adrs<28>) & ( adrs<27>) : r_data = cell0_3[adrs<26:0>] || cell1_3[adrs<26:0>] || cell2_3[adrs<26:0>] || cell3_3[adrs<26:0>] ; ( adrs<29>) & (^adrs<28>) & (^adrs<27>) : r_data = cell0_4[adrs<26:0>] || cell1_4[adrs<26:0>] || cell2_4[adrs<26:0>] || cell3_4[adrs<26:0>] ; ( adrs<29>) & (^adrs<28>) & ( adrs<27>) : r_data = cell0_5[adrs<26:0>] || cell1_5[adrs<26:0>] || cell2_5[adrs<26:0>] || cell3_5[adrs<26:0>] ; ( adrs<29>) & ( adrs<28>) & (^adrs<27>) : r_data = cell0_6[adrs<26:0>] || cell1_6[adrs<26:0>] || cell2_6[adrs<26:0>] || cell3_6[adrs<26:0>] ; ( adrs<29>) & ( adrs<28>) & ( adrs<27>) : r_data = cell0_7[adrs<26:0>] || cell1_7[adrs<26:0>] || cell2_7[adrs<26:0>] || cell3_7[adrs<26:0>] ; } instruct write any { (^adrs<29>) & (^adrs<28>) & (^adrs<27>) : any { byte_loc<0> : cell0[adrs<26:0>] := w_data<31:24> ; /* Lower Address */ byte_loc<1> : cell1[adrs<26:0>] := w_data<23:16> ; byte_loc<2> : cell2[adrs<26:0>] := w_data<15:8> ; byte_loc<3> : cell3[adrs<26:0>] := w_data<7:0> ; /* Upper Address */ } (^adrs<29>) & (^adrs<28>) & ( adrs<27>) : any { byte_loc<0> : cell0_1[adrs<26:0>] := w_data<31:24> ; /* Lower Address */ byte_loc<1> : cell1_1[adrs<26:0>] := w_data<23:16> ; byte_loc<2> : cell2_1[adrs<26:0>] := w_data<15:8> ; byte_loc<3> : cell3_1[adrs<26:0>] := w_data<7:0> ; /* Upper Address */ } (^adrs<29>) & ( adrs<28>) & (^adrs<27>) : any { byte_loc<0> : cell0_2[adrs<26:0>] := w_data<31:24> ; /* Lower Address */ byte_loc<1> : cell1_2[adrs<26:0>] := w_data<23:16> ; byte_loc<2> : cell2_2[adrs<26:0>] := w_data<15:8> ; byte_loc<3> : cell3_2[adrs<26:0>] := w_data<7:0> ; /* Upper Address */ } (^adrs<29>) & ( adrs<28>) & ( adrs<27>) : any { byte_loc<0> : cell0_3[adrs<26:0>] := w_data<31:24> ; /* Lower Address */ byte_loc<1> : cell1_3[adrs<26:0>] := w_data<23:16> ; byte_loc<2> : cell2_3[adrs<26:0>] := w_data<15:8> ; byte_loc<3> : cell3_3[adrs<26:0>] := w_data<7:0> ; /* Upper Address */ } ( adrs<29>) & (^adrs<28>) & (^adrs<27>) : any { byte_loc<0> : cell0_4[adrs<26:0>] := w_data<31:24> ; /* Lower Address */ byte_loc<1> : cell1_4[adrs<26:0>] := w_data<23:16> ; byte_loc<2> : cell2_4[adrs<26:0>] := w_data<15:8> ; byte_loc<3> : cell3_4[adrs<26:0>] := w_data<7:0> ; /* Upper Address */ } ( adrs<29>) & (^adrs<28>) & ( adrs<27>) : any { byte_loc<0> : cell0_5[adrs<26:0>] := w_data<31:24> ; /* Lower Address */ byte_loc<1> : cell1_5[adrs<26:0>] := w_data<23:16> ; byte_loc<2> : cell2_5[adrs<26:0>] := w_data<15:8> ; byte_loc<3> : cell3_5[adrs<26:0>] := w_data<7:0> ; /* Upper Address */ } ( adrs<29>) & ( adrs<28>) & (^adrs<27>) : any { byte_loc<0> : cell0_6[adrs<26:0>] := w_data<31:24> ; /* Lower Address */ byte_loc<1> : cell1_6[adrs<26:0>] := w_data<23:16> ; byte_loc<2> : cell2_6[adrs<26:0>] := w_data<15:8> ; byte_loc<3> : cell3_6[adrs<26:0>] := w_data<7:0> ; /* Upper Address */ } ( adrs<29>) & ( adrs<28>) & ( adrs<27>) : any { byte_loc<0> : cell0_7[adrs<26:0>] := w_data<31:24> ; /* Lower Address */ byte_loc<1> : cell1_7[adrs<26:0>] := w_data<23:16> ; byte_loc<2> : cell2_7[adrs<26:0>] := w_data<15:8> ; byte_loc<3> : cell3_7[adrs<26:0>] := w_data<7:0> ; /* Upper Address */ } } } instrin reset ; i_memory i_mem ; o_memory o_mem ; newcpu newcpu ; instruct reset newcpu.reset() ; instruct newcpu.i_read newcpu.ir_data = i_mem.read(newcpu.ir_adrs<31:2>).r_data ; instruct newcpu.o_read newcpu.or_data = o_mem.read(newcpu.rw_adrs<31:2>).r_data ; instruct newcpu.o_write o_mem.write(newcpu.rw_adrs<31:2>, newcpu.ow_loc, newcpu.ow_data) ; }