Read Me First!


It is sixteen years since we researched and developed PARTHENON. Sixteen years ago, I proposed to start the research and development of this design automation system from my research experience of mainframe processors called Denden Information Processing System (DIPS). That is because the higher level CAD, which is the best to design processors on architecture level and is able to manage the manufacturing process, were highly necessary at NTT, where do not have manufacture section of its own.

As a supervisor, I am going to introduce the history of PARTHENON and philosophy of its development. And hopefully, this will give people to know the spirit of this purely Japan-made technology and more useful information about PARTHENON.

This home page is based on the manual called "PARTHENON for the First Time" for PARTHENON/CQ version. In addition, we included the information: Its slide show for introduction, prescribed specifications of ASIC design contest (KUE-CHIP2, PCI bus interface), design exercise by PARTHENON, Frequently Asked Questions (FAQ), cell libraries and netlist converting tools for FPGAs (ALTERA, XILINX), and other related information.

I tried to edit the latest information to use PARTHENON as complete as possible. PARTHENON was researched and developed for both improvement of expression and expansion of design automation capability. I cannot stop hoping that people would understand new design nature of PARTHENON and create excellent architectures from Japan.

I edited this home page as a supervisor. Chapter 3, 4, and some part of chap.6 were written by Mr. Oguri. Mr. Nagoya wrote chapter 1, 2-3, 2-4, 7, 8, 9, 10 and slide shows. Mr. Nomura wrote chapter 2-1, 2-2, 5. The rest of chapter 6 was written by Mr. Yukishita. The prescribed specifications, "KUE-CHIP2", of ASIC design contest by Mr. Shiozawa, FAQ and FTP site by Mr. Suyama, design exercise by KUE-CHIP2 by Mr. Sawada. Mr. Ito gave the description examples of SFL. Mr. Matsuura made a list of PARTHENON related magazines. Mr. Nagami for the prescribed specifications, "PCI bus interface", and Mr. Yamashita for a list of references. And finally, Mr. Nagoya collected and edited them, and converted to HTML with Mr. Ito.

I would like to thank all the people who helped us: Mr. Kiyoshi Yamamoto and Mr. Hisaki Masuda from CQ Publishing Co., Ltd., Prof. Hideharu Amano of Keio University, who helped to collect examples from PARTHENON users, and Ms. Chifumi Oki as a secretary.

Yukihiro Nakamura
Executive Manager
High-speed Computer Networking Laboratory
NTT Information and Communication Systems Laboratories
March 1996


Following above, Mr. Konishi for FAQ, Mr. Nagano for netlist converting tools for FPGAs and Mr. Imlig for helpful information in English participate in updating this home page. And we also thank people from PARTHENON Technical Society, who are agreed to report activities related to the society, Dr. Mario Cardona for Spanish translation, and Aseed Systems Inc., NTT Advanced Technology Corp., Ms. Ayako Hasegawa and Ms. Yukiko Nakakouji for English translation.

Kiyoshi Oguri of NTT Network Innovation Laboratories
Akira Nagoya of NTT Communication Science Laboratories
January 1999

Some tools, such as netlist converting tools for FPGAs, are included in this home page, which can be cited from the other people for users' convenience. Please follow the regulations as described in README file when you use them. The copyright of design examples from PARTHENON users is reserved to each user, who creates them.

Back to "What is PARTHENON?"

Back to Home Page