Major PARTHENON programs and their functions are illustrated below.
<Fig.1.1> Flow-path of LSI Design using PARTHENON
SECONDS : An interactive behavioral simulation program for the SFL language, which directly interprets and executes the behavior flow described in SFL. It is used to verify that the SFL description faithfully reflects the designer's intention.
SFLEXP : A logic synthesis program that generates a technology-independent netlist from the SFL description (i.e. independent of the semiconductor device to be eventually mapped).
OPT_MAP : A mapping and logic circuit optimizing program that converts a technology-independent netlist into a technology-dependent netlist of real parts (technology mapping). It generates a final netlist to be entered into an LSI placement and routing program or an FPGA mapping tool. This process includes removal of unnecessary circuits, control of design hierarchy, optimization of timing conditions and other features.
ONSET : A logic circuit simplification program that reduces circuit size and delay time.
RINV : A polarity optimization program for global reduction in NOT gates (inverters) over the entire hierarchical logic circuit.
NLD_PS : A circuit diagram generation program that generates circuit diagrams in PostScript from the NLD formatted netlist (netlist format of PARTHENON). It prints circuit diagrams on a PostScript printer. In addition, the user can use a viewer program, such as Ghostscript, to display circuit diagrams on a screen and print them on a non-PostScript printer.
Figure 1.1 shows the LSI design flow using these programs. The designer can improve the design at an architecture level using SECONDS. When you have verified intended behavior at this stage of SFL description, you have already completed the greatest part of the design process. You can leave the programs to do almost all the remaining logical synthesis process. The final output is the final netlist and circuit diagrams.
PARTHENON allows you to fully benefit from so-called top-down design and concentrate on design work at the architectural level using SFL.
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