--- simulation modules: dec8 (circuit ) timer8 (module ) --- facilities of top module: / (module ) COUNT (term output ) DEC (submodule ) ENABLE (instr output ) EXPIRE (instr output ) INIT (term input ) MAIN (stage ) REMAINED (register ) RESET (instr input ) SET (instr input ) 1 (par statement ) --- simulation start: input pins | internal state, signals | output pins CLK SET RESET INIT| MAIN.RUN MAIN REMAINED| EXPIRE ENABLE COUNT ------------------------------------------------------------------ 1 1 0 04 | 0 DOWN uu | 0 0 zz 2 0 0 zz | 1 DOWN 04 | 0 1 04 3 0 0 zz | 1 DOWN 03 | 0 1 03 4 0 0 zz | 1 DOWN 02 | 0 1 02 5 0 0 zz | 1 DOWN 01 | 0 1 01 6 0 0 zz | 1 ASSERT 00 | 1 1 00 7 0 0 zz | 1 ASSERT 00 | 1 1 00 8 0 0 zz | 1 ASSERT 00 | 1 1 00 9 0 1 zz | 1 ASSERT 00 | 0 0 zz 10 0 0 zz | 0 DOWN 00 | 0 0 zz 11 1 0 ff | 0 DOWN 00 | 0 0 zz 12 0 0 zz | 1 DOWN ff | 0 1 ff 13 0 0 zz | 1 DOWN fe | 0 1 fe 14 0 1 zz | 1 DOWN fd | 0 0 zz 15 0 0 zz | 0 DOWN fd | 0 0 zz